Method for producing via-connections in a substrate and substrate equipped with same

ABSTRACT

A method of fabricating conducting through-connections in a substrate, and a substrate equipped with such connections. The method of fabricating conducting through-connections between the front face and the rear face of a substrate hollows into the substrate, from the rear-face side, cavities having a depth and a cross-section that are defined so as to delimit studs of defined cross-section, which are intended to provide for electrical conduction between the front and rear faces, and filling in the cavities with a dielectric material. The substrate is equipped with conducting through-connections between its front face and its rear face. The conducting connections are provided by way of studs delimited by cavities filled in with a dielectric material. Such a method and substrate may find application, in particular, to substrates used for the fabrication of microsensors.

TITLE OF THE INVENTION

The invention relates to a method of fabricating conductingthrough-connections between the front face and the rear face of asubstrate, as well as a substrate equipped with such conductingconnections.

BACKGROUND OF THE INVENTION

The invention applies especially to substrates intended to accommodate amicroelectronics structure, such as a sensor, a magnetic head or amicroactuator, or intended to accommodate a microelectronics circuit.

The substrate may be electrically conducting (for example made ofsilicon, or of polysilicon) or insulating (for example made of ceramic).

The conducting through-connections make it possible to provide discreteelectrical contacts between the front face and the rear face of asemiconducting, insulating or conducting substrate.

The use of conducting through-connections makes it possible:

to have a denser number of electrical contacts,

to provide electrical contacts over a stack of substrates,

to supply the components electrically from the rear face of thesubstrate when the wiring cannot be done on the front face.

The technique widely used to fabricate these conducting connectionsconsists in piercing the substrate from front to back (for example bylaser firing), in electrically insulating the hole (in the case of asemiconducting or conducting substrate) and in filling in the hole witha conducting material.

In the majority of applications, the filling of the holes has to becomplete in order to allow the electrical contact to be picked upeasily, in order to continue the technological stages relating to thefront and rear faces after the fabrication of the conducting connectionsand in order to allow the electrical contact to be taken up after anythinning of the substrate at the end of the process.

The filling is generally done with a conducting paste injected underpressure (method used to form microelectronics packages). Althougheffective, this technique is fairly “violent” and gives rise to defectson the faces of the substrate (splinters, roughness, cracks, stresses,etc). This technique can even entail a loss of insulation in the case ofsemiconducting substrates. Furthermore, the paste is made up of metallicparticles mixed with a solution based on polymers and solvents. Thissolution, which serves as a binder, has to be removed after filling.This removal causes a not inconsiderable shrinkage of the conductingmaterial which can be the origin of holes which are responsible for lossof conduction. The paste may also be the origin of contamination, thepolymers being difficult to remove.

Other techniques have been envisaged, in particular those described inthe document “Electrical Interconnections Through Semiconductor Wafers”by T. R. Anthony, published in the magazine Journal Application ofPhysic 52(8) of August 1981. It covers:

the use of electrolysis methods, which generally lead to a surfacefilling of the hole due to problems of wetting and of edge effects or

the filling by a molten metal. This technique poses problems of thermalexpansion. Metals with a low melting point (below the softeningtemperature of the substrate) exhibit a high coefficient of thermalexpansion, often much higher than the substrate. This results indifficulties of a mechanical nature (stresses) or technological nature(risk of cracking of the deposited layers).

One of the objects of the invention is to alleviate the abovementioneddrawbacks.

To that end, the subject of the invention is a method of fabricatingconducting through-connections between the front face and the rear faceof a substrate. The method consists:

in hollowing into the substrate, from the rear-face side, cavitieshaving a depth and a cross section which are defined so as to delimitstuds of defined cross section which are intended to provide forelectrical conduction between the two faces and

in filling in the cavities with a dielectric material.

A further subject of the invention is a substrate equipped withconducting through-connections between its front face and its rear face.The conducting connections consist of studs delimited by the hollowingof cavities, in the rear face of the substrate. These cavities arefilled in with a dielectric material.

The method consists in forming the conducting through-connections bydelimiting in the substrate (semiconducting, insulating or conductingsubstrate) studs which will serve as conducting passages between therear face and the front face of the substrate. The delimiting isperformed by hollowing out cavities. The cavities are filled in with adielectric material in order to provide for the mechanical strength andthe electrical insulation of the studs.

The use of an insulant as a material for filling the hollowed cavitiespresents the advantage of offering a coefficient of thermal expansionclose to that of the substrates widely used in microelectronics.

Furthermore, after filling, a thinning of the substrate on the two facesmakes it possible to remove the short circuits due to the substrate andthe surpluses of filling material.

The invention moreover has the advantage that it allows:

easy picking-up of the electrical contact, even after thinning of thesubstrate, and

very good electrical insulation of the conducting passages.

The substrate may be insulating (for example of ceramic) or slightlyconducting (for example of lightly doped semiconductor). In these casesa metallic deposit is formed or can be formed on the studs beforefilling of the cavities in order to provide the electrical conductivityof the studs.

In the case of the use of a silicon substrate of silicon-on-insulatortype, better known by the acronym SOI, the thinning of the substratewhich is intended to cut the short circuits after filling can bereplaced by etching of the silicon and oxide layers on the front-faceside in order to make the studs show through.

A substrate equipped with conducting through-connections which areobtained by a method according to the invention can play a part indelimiting an enclosure. The substrate may make it possible to seal theenclosure in such a way that the atmosphere in the enclosure isperfectly defined with, in particular, a pressure capable of being usedas a reference pressure. The leaktightness of the substrate is not inany way affected by the conducting through-connections consisting of thestuds. This is because, on the one hand, the conductingthrough-connections obtained by a method according to the inventionleave the front face of the substrate perfectly flat and, on the otherhand, the dielectric material fills in the cavity in a completelyhermetic way. The possibility of being able to carry out sealing plays avital role, in particular for the fabrication of microsensors.

BRIEF DESCRIPTION OF THE DRAWINGS

Other characteristics and advantages of the invention will emerge withthe aid of the description which follows. The description is given withregard to the annexed figures which represent:

FIG. 1, a substrate on completion of a first stage of the method,

FIG. 2, a magnification of a stud,

FIG. 3, a substrate on completion of a second stage of the method,

FIG. 4, a substrate on completion of a third stage of the method,

FIG. 5, a substrate on completion of a fourth stage of the method,

FIG. 6, a substrate on completion of a fifth stage of the method,

FIG. 7, a substrate on completion of a sixth stage of the method,

FIG. 8, a substrate on completion of a seventh stage of the method,

FIGS. 9 to 14, the stages of the method implemented with a substrateconsisting of a stack of layers.

DETAILED DESCRIPTION

FIG. 1 represents a substrate 1 having a front face 2 and a rear face 3.The substrate 1 is usually of silicon, but it may be of another type,ceramic for example. The method according to the invention appliesequally well to a slightly conducting substrate (a semiconductor such assilicon, possibly doped), and to an insulating (ceramic) substrate orelse to a conducting substrate.

The first stage of the method consists in delimiting studs 4 in thesubstrate 1. These studs 4 are intended to provide an electricalconnection through the substrate 1. The studs 4 are advantageouslyformed in the substrate 1 itself.

The delimiting of a stud 4 is performed by hollowing out a cavity 5 inthe rear face 3 of the substrate 1. According to the example of FIG. 1,the cavity 5 has a ring-shaped circular cross section. This ring has awidth I_(d) and a diameter 2×(I_(p)+I_(d)) with a solid part of diameter2×I_(p) which constitutes the stud. The cavity 5 has a depth Pd lessthan the thickness e of the substrate 1. The cross section of the cavity5 may not be circular, but square, rectangular, etc. The same goes forthe cross section of the stud 4, the cross section of the stud possiblybeing of a different shape to that of the cavity.

The hollowing of a cavity 5 is achieved by known techniques. One of theknown techniques consists, with the aid of a mask, for example, made ofresin or of oxide, in carrying out dry anisotropic etching. Anotherknown technique consists, with the aid of a mask, in carrying outchemical etching. For a silicon substrate of thickness e=525 μm, thedepth P_(d) of the cavity 5 is of the order of 300 μm. For a ceramicsubstrate, the hollowing is generally performed by mechanical machiningof the substrate.

FIG. 2 is a magnification of a stud. The stud 4, of diameter 2×I_(p), isdelimited by the cavity 5 in the shape of a cylindrical ring of widthI_(d). For example, the stud 4 has a diameter 2×I_(p)=50 μm and thecavity 5 a width I_(d)=50 μm.

FIG. 3 illustrates the second stage of the method. This second stage isoptional; it is necessary when the substrate 1 is not sufficientlyconducting, for example in the case of a ceramic substrate. This stageconsists in carrying out the depositing of a thin conducting layer 6which has the function of increasing the conductivity of the stud.Depending on the technique used to carry out the deposition, the layer 6is deposited only on the rear face or else simultaneously on the twofaces.

The technique used should allow a deposition over the entire heightP_(d) of the stud. On completion of this stage, the surface of the rearface, and possibly of the front face, is completely covered with a thinconducting layer; the surface of the rear face comprising the surface ofthe studs 4 as far as the bottom of the cavities 5. A technique ofchemical deposition in vapor phase, for example of tungsten (W), makesit possible to obtain a deposition of a conducting layer 6 in accordancewith the above description. Such a technique is known by the acronymCVD, an abbreviation of the term Chemical Vapor Deposition.

FIG. 4 illustrates the third stage of the method. The cavities 5 arefilled in with a defined material 7. The material 7 should be insulatingor only slightly conducting in order to insulate the stud from the restof the substrate 1 when the latter is conducting. The depositiontechnique consists typically in deposition by melting. The method makesit possible to use materials having a low coefficient of thermalexpansion. The material may advantageously have a coefficient of thermalexpansion very close to that of the silicon, in the case of a siliconsubstrate, while having a melting temperature less than that of thesilicon. The low coefficient of thermal expansion makes it possible toavoid the awkward problems relating to the difference in coefficient ofthermal expansion between the filling material and the substrate;problems with which certain known connection techniques are confronted.

The material adopted may be glass, deposited by melting.

The material 7, in addition to an insulation function which is necessarywhen the substrate is conducting, performs a function of retention ofthe stud 4. The material 7 integrates the stud 4 over its height withthe substrate 1. The material 7 may, moreover, participate in delimitinga sealed enclosure.

Depending on the deposition techniques used, the material deposited maycover the whole of the rear face as FIG. 4 illustrates.

FIG. 5 illustrates the fourth stage of the method.

This stage makes it possible to uncover the substrate by removing theunwanted surface layers. When the dielectric 7 overflows from thecavities 5, it has to be removed by thinning the rear face 3 of thesubstrate 1. The thinning may consist of a lapping, polishing, etchingor a combination of these various techniques. Lapping consists inabrasion which has the drawback of leaving a surface having a scratchedsurface state. In order to remedy this drawback, the abrasion isfollowed by polishing in order to obtain a smooth surface state. Onepolishing technique is widely known by the acronym CMP, an abbreviationof the term Chemical Mechanical Planarization. This technique has adouble effect, mechanical and chemical, which makes it possible toobtain a smooth surface. The polishing is particularly important whenthe second stage has not been implemented, that is to say when there hasbeen no deposition of a conducting layer. The etching may consist of dryor wet etching. Dry etching employs a plasma, wet etching employs achemical bath.

The thinning described above may make it possible to remove theconducting layer (deposited during the second stage) from the rear face3 and from the front face 2 if the conducting layer is present on thelatter. The removal of the conducting layer can be carried out in anindependent or supplementary way by a known specific technique, forexample by dry etching or wet etching. The dry etching may be of the RIEtype, an abbreviation of the term Reactive Ion Etching.

On completion of the fourth stage, the substrate comprises a set ofstuds 4. This set may comprise a single stud 4. The maximum density ofstuds capable of being delimited in a substrate of given size depends,in particular, on the performance of the etching technique used duringthe first stage. The cavities 5, filled in with a dielectric material 7,provide the mechanical strength and the electrical insulation of thestuds 4. The material 7 may, moreover, participate in delimiting asealed enclosure. The use of a dielectric as a material for filling thehollowed cavities presents the advantage of offering a coefficient ofthermal expansion similar to that of the substrates widely used inmicroelectronics. The method makes it possible to solve the problemsrelating to the difference in coefficient of thermal expansion betweenthe substrate and the filling material. The method overcomes problems ofremoval and of contamination, moreover.

The fifth stage, FIG. 6, makes it possible to eliminate the shortcircuit between the stud 4 and the front face 2 of the substrate 1. Theelimination is performed by a thinning of the front face according to aknown technique. A first technique may consist in lapping, by abrasion,the front face 2 of the substrate 1; a second technique may consist ofdry or wet etching; a third technique may consist of a combination oflapping, etching and polishing. The studs 4, possibly metallized 6, areconducting elements which make it possible to establish electricalthrough-connections between the two faces 2, 3 of the substrate 1. Thefront face 2 of the substrate 1 is generally intended for theinstallation of an electronic function or of a microstructure, amicrosensor for example. The studs 4 make it possible, for example, tosupply the microsensor electrically via the rear face 3 by providing anelectrical connection between the rear face 3 and points of contactwithin the circuit of the microsensor. The studs 4 make it possible tohave available contact points which do not affect the flatness of thesurface of the front face 2 of the substrate 1. A substrate 1, equippedwith studs 4 obtained according to a method according to the invention,may contribute to delimiting an enclosure. The substrate may make itpossible to achieve sealing of the enclosure in such a way that theatmosphere in the enclosure is perfectly defined with, in particular, apressure possibly being used as a reference pressure. The leaktightnessof the enclosure is not in any way affected by the conductingthrough-connections consisting of the studs. In fact, on completion ofthe fifth stage, the front face 2 of the substrate 1 is perfectly flat.

The sixth stage, FIG. 7, consists in depositing a thin insulating layer8 on the two faces 2, 3 of the substrate 1 and in opening up contactregions 9 opposite the studs 4. The deposition of a thin insulatinglayer 8 is performed by a known technique, for example of the plasmatype such as the technique known by the acronym PECVD, an abbreviationof the term Plasma Enhance Chemical Vapor Deposition.

The opening of the contact regions 9 can be performed by masking andetching of the insulating layer 8. The masking can be carried out byphotolithography.

The seventh stage, FIG. 8, consists in physically forming the points 10of contact opposite the studs 4. The physical forming is carried out byknown techniques which consist in depositing a thin conducting layer 11on the two faces 2, 3 of the substrate 1 and in cutting out the points10, for example by masking and etching of the conducting layer 11. Themasking can be carried out by photolithography.

FIGS. 9 to 14 illustrate an implementation of the method with asubstrate consisting of a stack of layers. This substrate 1 may be ofSOI type, an abbreviation of the term Silicon On Insulator. The firstlayer 12 of the stack consists of silicon. The free face of the firstlayer corresponds to the rear face 3 of the substrate. The second layer13 of the stack is an insulating layer. It consists of a silicon oxide.The third layer 14 of the stack consists of silicon. Its free facecorresponds to the front face 2 of the substrate. An SOI substrate hasthe following thicknesses, for example:

1^(st) layer: 500 μm

2^(nd) layer: 0.4 μm

3^(rd) layer: from 0.2 μm to several μm.

The third layer 14 is generally reserved for the fabrication ofelectronic functions or for the implementation of microstructures, forexample a microsensor, a microactuator, etc.

FIG. 9 illustrates the first stage of the method. According to thisimplementation, the cavities 5 are hollowed until the insulating layer13 is uncovered.

When the method is implemented with a substrate of SOI type, the secondstage does not exist.

FIG. 10 illustrates the third stage of the method. The type of substratedoes not alter the implementation of the third stage; this stageprogresses according to the description given with regard to FIG. 4.

FIG. 11 illustrates the fourth stage of the method. The type ofsubstrate does not alter the implementation of the fourth stage; thisstage progresses according to the description given with regard to FIG.5.

When the method is implemented with a substrate consisting of a stack oflayers, in particular of the SOI type, the fifth stage does not exist.

FIG. 12 illustrates the sixth stage of the method. Given that the studs4 are not visible on the front face 2, the depositing of the thininsulating layer 8 is performed only on the rear face 3. The depositingprogresses according to the description given with regard to FIG. 7,with, as a limitation, a deposition on the rear face 3.

FIG. 13 illustrates the seventh stage of the method. The implementationis different from that described with regard to FIG. 8 to the extentthat the points 10 of contact are present only on the rear face 3.

In order to obtain a through-stud, supplementary stages are necessary.They are illustrated by FIG. 14. They consist:

in etching the third layer 14 and the second layer 13 from the frontface 2 by using a mask. The etching is carried out as far as the stud 4,according to a technique identical to that described with regard to FIG.1, in order to uncover the stud and only a part of the dielectric.

in physically forming the points 10 of contact on the front face 2according to a technique similar to that described with regard to FIG.13. In the case of the points 10 of contact on the front face, the crosssection of etching of the insulating layer 8 is less than the crosssection of etching of the third and second layers of the substrate.

What is claimed is:
 1. A method of fabricating conductingthrough-connections between a front face and a rear face of a substrate,comprising: hollowing into the rear face of the substrate a cavity thatsurrounds a stud of substrate material formed by the cavity thatprovides for electrical conduction between the front and rear faces;filling in the cavity with a dielectric material to insulate the studfrom a rest of the substrate and to integrate the stud with thesubstrate while allowing the stud to show through the rear face;hollowing the front face of the substrate opposite each stud so as tomake the stud show through the front face thereby converting the studinto a conducting through-connection; and physically forming points ofcontact at each end of the stud showing through the substrate bydepositing a conducting material, insulated from the substrate, on eachof these ends.
 2. The method of fabricating conductingthrough-connections between the front face and the rear face of asubstrate as claimed in claim 1, wherein the filling of the cavitycomprises: depositing the dielectric material in the cavity; andremoving, from a surface of the substrate, overflows of the deposit ofdielectric material by thinning the rear face of the substrate until thestud is uncovered.
 3. The method of fabricating conductingthrough-connections between the front face and the rear face of asubstrate as claimed in claim 1, further comprising, after forming thestud and before filling in the cavity: metallizing the stud bydepositing a conducting layer on the stud.
 4. The method of fabricatingconducting through-connections between the front face and the rear faceof a substrate as claimed in claim 3, wherein the filling-in of thecavity comprises: depositing the dielectric material in the cavity;removing, from a surface of the substrate, overflows of the deposit ofthe dielectric material by thinning the rear face of the substrate untilthe stud is uncovered; and removing the conducting layer from thesurface of the substrate, by thinning of the metallized faces of thesubstrate.
 5. The method of fabricating conducting through-connectionsbetween the front face and the rear face of a substrate as claimed inclaim 1, further comprising: thinning the substrate until the dielectricmaterial contained in the cavity is uncovered so as to make the studshow through on the front face of the substrate.
 6. The method offabricating conducting through-connections between the front face andthe rear face of a substrate as claimed in claim 1, further comprising:hollowing the front face of the substrate opposite the stud until thedielectric material contained in the cavity is reached, so as to makethe stud show through on the front face of the substrate.
 7. The methodof fabricating conducting through-connections between the front face andthe rear face of a substrate as claimed in claim 1, wherein the physicalformation of the points of contact comprises: depositing an insulatinglayer on a same side as the faces of the stud showing through; openingup a contact region opposite each face of the stud showing through bymasking and etching of the insulating layer; depositing a conductinglayer on the same side as the faces of the stud showing through; andcutting out the points of contact by masking and etching of theconducting layer.
 8. The method of fabricating conductingthrough-connections between the front face and the rear face of asubstrate as claimed in claim 1, wherein the dielectric filling materialis glass.
 9. The method of fabricating conducting through connectionsbetween a front from a rear face of a substrate as claimed in claim 1,wherein said hollowing into the substrate, said filling in the cavity,said hollowing the front face of the substrate, and said physicallyforming steps are performed at a plurality of areas of the substrate inorder to form a plurality of conducting-through connections.
 10. Asubstrate of silicon equipped with a conducting through-connectionbetween a front face and a rear face of the substrate, wherein; theconducting through-connection comprises a stud of the substrate ofsilicon that extends over an entire height of the substrate and issurrounded by a dielectric material which delimits the stud and keepsthe stud integral with the substrate, the stud showing through on thefront and rear faces of the substrate, and points of contact beingformed opposite each face showing through of the stud by a conductingmaterial insulated from the substrate.
 11. The substrate as claimed inclaim 10, wherein the silicon stud is coated substantially over itsentire height by a conducting metallization that is surrounded by thedielectric material.
 12. The substrate as claimed in claim 10, whereinsaid substrate comprises a plurality of said through-connections.